BCM8210 ? 2.488 gbps fully integrated low power sonet/sdh transceiver application block diagram ? fully integrated oc-48/stm-16 sonet/sdh transceiver with cdr, mux, demux, and cmu 16-bit, 155.52-mbps lvpecl interfaceuse bullet for these on-chip, pll-based clock generator loss-of-signal (losb) output line and system loopback modes lock detect meets sonet, telcordia, and itu-t jitter requirements power supply: 2.5v (core), 3.3v (lvpecl i/o) power dissipation: 1.2w typical 14 20 mm,128-pin pqfp package standard cmos fabrication process first cmos oc-48 transceiver in the world. low power consumption eliminates external heat sink, fans for system airflow, and expensive high current power supplies. high integration reduces design cycle and time to market. increased port density per board and system. cmos-based device takes advantage of the most effective silicon economy of scale. features low-jitter cmu: 3 muirms typical. target applications: oc-48/stm-16 transmission equipment sonet/sdh optical modules and test equipment add/drop multiplexers digital cross-connects atm switch backbones terabit routers edge routers features summary of benefits 155 . 52 m bp s 2 . 488 g bp s 155 . 52 m bp s n e t wo r k i n t e r f ace p r o cess o r n e t wo r k i n t e r f ace p r o cess o r otx o r x o r x otx bcm 8 210 bcm 8 210 16 16 16 16
BCM8210 overview ? phone: 949-450-8700 fax: 949-450-8710 e-mail: info@broadcom.com web: www.broadcom.com broadcom corporation 16215 alton parkway, p.o. box 57013 irvine, california 92619-7013 ? 2004 by broadcom corporation. all rights reserved. 8210-pb07-r 04/15/03 broadcom ? , the pulse logo, and connecting everything ? are trademarks of broadcom corporation and/ or its subsidiaries in the united states and certain other countries. all other trademarks mentioned are the property of their respective owners. the BCM8210 sonet/sdh transceiver is a fully integrated serialization/deserial ization sonet oc-48 and stm sdh-16 (2.488 gbps) interface device with an integrated clock multiplication unit (cmu) and an integrated clock and data recovery circuit (cdr). on- chip clock synthesis is performed by the high-frequency, low-jitter, phase-locked loop on the BCM8210 transceiver chip, allowing the use of a slower 77.76 mhz external transmit clock reference. clock recovery is performed on the device by synchronizing its on-chip vco directly to the incoming data stream. the low-jitter lvpecl interface guarantees compliance with the bit error rate requirements of the telcordia gr-253- core, ansi, and itu-t standards. the BCM8210 is packaged in a 14 20 mm, 128-pin pqfp. transmitter functions 16-bit parallel input 2.488-ghz clock generation elastic buffering parallel-to-serial conversion serial differential data output receiver functions 16-bit parallel output 2.488-gbps differential data input clock and data recovery (cdr) serial-to-parallel conversion 16 x 5 fifo vcp_cdr vcn_cdr resetb clk16ip clk16in di0 di15 refckp refckn rdinp rdinn lpbkfb lpbksb txdp txdn txckp txckn tck16o losb do0 do15 rck16op rck16on lckdet fifo control write pointer read pointer output retime input register 2.488-ghz pll divide-by-16 16:1 parallel- to-serial los detect 1:16 serial- to-parallel output register divide-by-16 cdr loop- back logic
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